Recently, in the field of display systems, displays that use various display devices, such as a liquid crystal display system and a display that uses organic EL (Electro Luminescence) elements, have been developed. Higher image quality (increased gray scales) is demanded for these display systems, and voltage amplitudes of a scan signal and a gray scale signal tend to be increased. For this reason, higher voltages of respective output sections of a row driver that drives a scan line of a display panel and a column driver that drives a data line of the display panel using the gray scale signal are demanded.
On the other hand, higher-speed transfer and low EMI (Electromagnetic Interference) or the like using a small number of signal lines are demanded for various control signals and image data signals supplied to the row driver (scan driver) and the column driver (data driver) from a display controller. Lower amplitudes of those signals are being achieved. Further, even in the row driver and the column driver, a fine fabrication process has been adopted in order to reduce an increase in the area (cost) of logic circuits that handle data, the amount of which increases accompanying a higher definition and the increased gray scales. With the fine fabrication process, the power supply voltage of each logic circuit tends to be reduced.
That is, lower voltages of input sections of the row driver and the column driver and higher voltages of the output sections of the row driver and the column driver are demanded.
For this reason, in a level shift circuit that converts a low-voltage signal in an input section thereof to a high-voltage signal in an output section thereof, a low-amplitude signal must be converted to a high-amplitude signal at high speed.
FIG. 13 is a diagram showing an example of a typical configuration of the level shift circuit that converts a low-amplitude signal to a high-amplitude signal (refer to Patent Document 1 listed below). This level shift circuit receives a low-voltage signal IN and outputs a high-voltage output signal OUT and a high-voltage output signal OUTB which is a reverse phase signal of the signal OUT. The level shift circuit includes P-channel MOS transistors P1 and P2 which have sources connected to a power supply terminal VDD3, have gates connected to output terminals W2 and W1, respectively, and have drains connected to the output terminals W1 and W2, respectively. The P-channel MOS transistors P1 and P2 function as charging elements for the output terminals W1 and W2, respectively. The P-channel MOS transistors P1 and P2 respectively receive at the gates thereof the high-amplitude output signal OUT output from the output terminal W2 and the output signal OUTB output from the output terminal W1. The maximum absolute value of a gate-to-source voltage VGS of each of the P-channel MOS transistors P1 and P2 is |VSS-VDD3|. N-channel MOS transistors N1 and N2 function as discharging elements for the output terminals W1 and W2, respectively. The N-channel MOS transistors N1 and N2 have sources connected to a power supply terminal VSS and have drains connected to the output terminals W1 and W2, respectively. The N-channel MOS transistors N1 and N2 respectively receive at gates thereof the low-voltage input signal IN and the inverted signal of the input signal IN (both being low-amplitude signals).
The maximum gate-to-source voltage of each of the discharging elements N1 and N2 is set to the amplitude of the input signal IN. Discharging capability of each of the discharging elements N1 and N2 is lower than charging capability of each of the charging elements P1 and P2 of which the maximum absolute value of the gate-to-source voltage VGS is |VSS-VDD3|. A drain current of each of the discharging elements N1 and N2 and the charging elements P1 and P2 is proportional to the square of [(gate-to-source voltage)−(threshold voltage)], for example. A drain current of each of the charging elements P1 and P2, whose gate-to-source voltage at an on time is set to a larger value, is larger than a drain current of each of the discharging elements N1 and N2.
Then, in order to increase discharging capability of the respective discharging elements N1 and N2, the element size of the respective discharging elements N1 and N2 (W/L ratio; where W is a channel width, and L is a channel length) needs to be sufficiently large.
By the way, the discharging capability of the respective discharging elements N1 and N2 must be set to exceed the charging capability of the respective charging elements P1 and P2. This can be readily understood in view of a discharging operation of the respective discharging elements N1 and N2.
As a specific example, a change from a state (initial state) where the output terminals W1 and W2 respectively have a potential VDD3, (which is a High potential) and a potential VSS, (which is a Low potential) will be considered, for example. In this state, the charging element P1 is in an on state, while the charging element P2 is in an off state. Further, the input signal IN is Low, the discharging element N1 is in an off state, and the discharging element N2 is in an on state.
Then, when the input signal IN is changed from a Low level to a High level, the discharging element N1 is turned on, and the discharging element N2 is turned off. However, the charging element P1 immediately after the change of the input signal IN from the Low level to the High level of a low amplitude is kept in the on state. Thus, in order to change the output terminal W1 to Low (VSS) by the discharging element N1, the discharging capacity of the discharging element N1 (drain current of the N-channel MOS transistor N1) needs to exceed the charging capability of the charging element P1 (drain current of the P-channel MOS transistor P1).
Accordingly, in order to cause the level shift circuit in FIG. 13 to operate normally, the element size (W/L ratio) of the respective discharging elements N1 and N2 must be set to be sufficiently large, and also the element size (W/L ratio) of the respective charging elements P1 and P2 must be set to be sufficiently small so that the discharging capability exceeds the charging capability.
That is, the size of each of the discharging elements in the level shift circuit in FIG. 13 is increased and the area of the level shift circuit is increased. Especially when operated at low voltage of the input signal IN, the discharging capability of the respective discharging elements N1 and N2 is relatively reduced. Thus, the circuit area will further increase.
Further, it becomes difficult to set the transistor size so that the discharging capability of the respective discharging elements N1 and N2 sufficiently exceeds the charging capability of the respective charging elements P1 and P2.
When the W/L ratios of the discharging elements N1 and N2 are increased, a level shift operation is slowed down due to an increase in parasitic capacitances. Thus, a time interval where the discharging element N1 and the charging element P1 are simultaneously in an on state or a time interval where the discharging element N2 and the charging element P2 are simultaneously in an on state is prolonged. Thus, there also arises a problem that short circuit current that flows transiently increases, so that power dissipation increases.
FIG. 14 is a diagram showing a configuration of a single-ended level shift circuit (refer to Patent Document 2 listed below). The single-ended level shift circuit includes an output-stage driver 12, a predriver 14, a feedback P-channel MOS transistor 16, a compensating N-channel MOS transistor 18, and a compensating N-channel MOS transistor 32. The output-stage driver 12 includes a P-channel MOS transistor 20 and an N-channel MOS transistor 22, and drives an output terminal OUT1 according to an output signal of the predriver 14. The P-channel MOS transistor 20 is connected between a high-potential power supply VCCH and the output terminal OUT1, and the N-channel MOS transistor 22 is connected between the output terminal OUT1 and the ground. Gates of the P-channel MOS transistor 20 and the N-channel MOS transistor 22 are connected to internal nodes N11 and N12, respectively. The predriver 14 includes a P-channel MOS transistor 24, an N-channel MOS transistor 26, and an N-channel MOS transistor 28, and drives the internal nodes N11 and N12 according to a signal supplied to an input terminal IN1. The P-channel MOS transistor 24 is connected between a low-potential power supply VCCL and the internal node N12. The N-channel MOS transistor 26 is connected between the internal node N12 and the ground, and the N-channel MOS transistor 28 is connected between the internal node N11 and the ground. Gates of the P-channel MOS transistor 24 and the N-channel MOS transistors 26 and 28 are all connected to the input terminal IN1. The feedback P-channel MOS transistor 16 is connected between the high-potential power supply VCCH and the internal node N11, has a gate connected to the output terminal OUT1, and drives the internal node N11 to a High level (high-potential power supply voltage VCCH) according to a signal driven to the output terminal OUT1. The compensating N-channel MOS transistor 18 is connected between the high-potential power supply VCCH and the internal node N11, has a gate connected to the internal node N12, and drives the internal node N11 to a High level (low-potential power supply voltage VCCL-threshold voltage VTH of N-channel MOS transistor 18) according to an output signal of the predriver 14. The N-channel MOS transistor 32 is connected between the high-potential power supply VCCH and the output terminal OUT1, and has a gate connected to the input terminal IN1.
In this level shift circuit, the compensating N-channel MOS transistor 18 is connected between the internal node N11 and the high-potential power supply VCCH, and the compensating N-channel MOS transistor 32 is connected between the output node OUT1 and the high-potential power supply VCCH. When an input signal IN1 is changed from Low to High, the compensating transistor 32 accelerates an increase in the potential at the output node OUT1 to a high voltage. When the input signal IN1 is changed from High to Low, the compensating transistor 18 accelerates an increase in the potential at the node N11. A level shift operation is thereby sped up.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2001-298356A    [Patent Document 2] JP Patent Kokai Publication No. JP-A-9-93114